1. Field of the Invention
The present invention relates to a yield evaluating apparatus and a method thereof.
2. Description of Related Art
Along with the advancement of semiconductor techniques, the sizes of electronic devices are getting smaller; however, process variations of these electronic devices and the affections thereof are getting more serious. As a result, product yield may be affected and yield loss may be resulted. Generally speaking, the major factors for causing yield loss are parametric yield and defect-related yield, wherein the parametric yield and the defect-related yield are respectively originated from process variations and defects.
In order to deal with these process variations which are difficult to control, many yield analysis and correction methods, such as the critical area analysis (CAA), the optical proximity correction (OPC), and the chemical mechanical polishing (CMP), etc, are provided by different EDA vendors. However, each of the foregoing analysis and correction methods requires the foundry to provide a process-related data, and corrections can only be carried out at the back-end level after the chip is taped-out. Thus, a chip designer has to revise the circuit layout or even adjust the circuit design in order to allow the product yield to reach a certain target. However, the product may not be brought into the market on time since it is very time-consuming to repeatedly correct the circuit layout or adjust the circuit design.
In order to observe the process variations at the design stage, information of the process variations is usually brought into circuit simulation through Monte-Carlo analysis. Thus, if the process variations can be taken into the consideration on the front-end level of the design flow, the affections thereof to the performance of the circuit can be found out at an early stage and accordingly the product can be brought into the market in a short time. However, it is very time-consuming to simulate the process variations through Monte-Carlo analysis directly in a circuit simulation software (for example, HSPICE), and the method may not be applicable if the circuit is very big.
Generally speaking, the performances of most hybrid or analog circuits are closely related to the element mismatching characteristics of these circuits. For example, the performance of a switched-capacitance circuit, such as an analog-to-digital converter, a digital-to-analog converter, a sampling circuit, or a filter, is directly related to the ratio of the capacitors thereof, wherein the ratio of the capacitors is related to the capacitor mismatching characteristic of the circuit. Thus, element mismatch is usually eliminated through a common centroid method in order to ensure the correctness of the elements.
When the common centroid method is adopted, the element array has to conform to a coincidence rule, a symmetry rule, a dispersion rule, and a compactness rule. The coincidence rule means that each unit element in the element array has to have the same size, the symmetry rule means that the element array has to be symmetric to axis X and axis Y, the dispersion rule means that the dispersion of each unit element in the element array should be uniform, and the compactness rule means that the element array should be very compact. However, the foregoing rules are only used as the layout reference and there is not any discriminant for determining how much an actual layout meets foregoing rules.
Accordingly, some related discriminants are provided for evaluating the common centroid rule. However, these discriminants only analyze the common centroid method according to relative positions between the elements but do not consider the process variations of the elements themselves. Besides, these discriminants are only applicable to rectangular layouts. Thereby, the mismatching results obtained through foregoing methods cannot reflect the actual quality of a circuit and the actual improvement in the product yield.